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| a FEATURES CMOS 8-Bit 32 MSPS Sampling A/D Converter Pin-Compatible with AD876-8 Power Dissipation: 95 mW (3 V Supply) Operation Between +2.7 V and +5.5 V Supply Differential Nonlinearity: 0.2 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp Function (DC Restore) Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT DESCRIPTION Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter AD9280 A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. The AD9280 can operate with a supply range from +2.7 V to +5.5 V, ideally suiting it for low power operation in high speed applications. The AD9280 is specified over the industrial (-40C to +85C) temperature range. PRODUCT HIGHLIGHTS Low Power The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9280 uses a multistage differential pipeline architecture at 32 MSPS data rates and guarantees no missing codes over the full operating temperature range. The input of the AD9280 has been designed to ease the development of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. The sample-and-hold amplifier (SHA) is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. AC-coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit. The dynamic performance is excellent. The AD9280 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The AD9280 consumes 95 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW. Very Small Package The AD9280 is available in a 28-lead SSOP package. Pin Compatible with AD876-8 The AD9280 is pin compatible with the AD876-8, allowing older designs to migrate to lower supply voltages. 300 MHz Onboard Sample-and-Hold The versatile SHA input can be configured for either singleended or differential inputs. Out-of-Range Indicator The OTR output bit indicates when the input signal is beyond the AD9280's input range. Built-In Clamp Function Allows dc restoration of video signals. FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP IN CLK AVDD DRVDD STBY SHA VINA REFTF REFTS REFBS REFBF OUTPUT BUFFERS VREF REFSENSE 1V A/D D/A A/D D/A A/D D/A A/D D/A SHA GAIN SHA GAIN SHA GAIN SHA GAIN A/D MODE THREESTATE CORRECTION LOGIC OTR D7 (MSB) D0 (LSB) AVSS DRVSS AD9280 REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD9280-SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage Reference Input Resistance1 ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (-3 dB) Full Power (0 dB) DC Leakage Current INTERNAL REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2 V Mode) Load Regulation (1 V Mode) POWER SUPPLY Operating Voltage Supply Current Power Consumption Power-Down Gain Error Power Supply Rejection FS DNL INL EZS EFS REFTS REFBS Symbol (AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted) Min Typ 8 32 0.2 0.3 0.2 1.2 1 GND 2 10 4.2 1.0 1.5 1.8 3.9 Max Units Bits MHz LSB LSB % FSR % FSR REFTS = 2.5 V, REFBS = 0.5 V Condition AVDD V AVDD - 1 V V p-p k k REFTS V pF ns ps MHz A V mV V mV V V mA mW mW % FS REFTS, REFBS: MODE = AVDD Between REFTF & REFBF: MODE = AVSS REFBS Min = GND: REFTS Max = AVDD Switched AIN CIN tAP tAJ BW REFBS 1 4 2 300 43 Input = FS REFSENSE = VREF REFSENSE = GND 1 mA Load Current VREF VREF 1 10 2 0.5 2.7 2.7 3 3 31.7 95 4 1 25 2 5.5 5.5 36.7 110 AVDD DRVDD IAVDD PD AVDD = 3 V, MODE = AVSS AVDD = DRVDD = 3 V, MODE = AVSS STBY = AVDD, MODE and CLOCK = AVSS PSRR DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz f = 16 MHz Effective Bits f = 3.58 MHz f = 16 MHz Signal-to-Noise SNR f = 3.58 MHz f = 16 MHz Total Harmonic Distortion THD f = 3.58 MHz f = 16 MHz Spurious Free Dynamic Range SFDR f = 3.58 MHz f = 16 MHz Differential Phase DP Differential Gain DG 46.4 49 48 7.8 7.7 dB dB Bits Bits dB dB -49.5 dB dB dB dB Degree % 47.8 49 48 -62 -58 66 61 0.2 0.08 51.4 NTSC 40 IRE Mod Ramp -2- REV. D AD9280 Parameter DIGITAL INPUTS High Input Voltage Low Input Voltage DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 A) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 A) LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 A) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 A) CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency CLAMP Clamp Error Voltage Clamp Pulsewidth NOTES 1 See Figures 1a and 1b. Specifications subject to change without notice. Symbol VIH VIL IOZ tOD tDEN tDHZ VOH VOH VOL VOL VOH VOH VOL VOL tCH tCL Min 2.4 Typ Max Units V V A ns ns ns V V V V V V V V ns ns Cycles Condition 0.3 -10 25 25 13 +2.95 +2.80 +0.4 +0.05 +4.5 +2.4 +0.4 +0.1 14.7 14.7 3 +10 Output = GND to VDD CL = 20 pF EOC tCPW 60 2 80 mV s CLAMPIN = +0.5 V to +2.0 V, RIN = 10 CIN = 1 F (Period = 63.5 s) 10k REFTS 10k REFBS REFTS AD9280 REFTF AD9280 4.2k REFBF 0.4 AVDD MODE VDD REFBS MODE a. Figure 1. Equivalent Input Load b. REV. D -3- AD9280 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -65 Max +6.5 +6.5 +0.3 +6.5 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 +300 Units V V V V V V V V V V V V C C C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD MODE AVSS CLK AVSS Digital Outputs DRVSS AIN AVSS VREF AVSS REFSENSE AVSS REFTF, REFTB AVSS REFTS, REFBS AVSS Junction Temperature Storage Temperature Lead Temperature 10 sec ORDERING GUIDE Temperature Range Package Description Package Option* Model AD9280ARS -40C to +85C 28-Lead SSOP RS-28 AD9280ARSRL -40C to +85C 28-Lead SSOP (Reel) RS-28 AD9280-EB Evaluation Board *RS = Shrink Small Outline. AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS DRVSS AVSS AVSS AVSS AVSS AVSS a. D0-D7, OTR b. Three-State, Standby, Clamp AVDD c. CLK AVDD AVDD REFBS 25 REFTF AVSS 22 AVSS AVDD AVDD REFBF AVSS 24 REFTS AVSS 21 AVSS d. AIN AVDD AVDD e. Reference AVDD AVDD AVSS AVSS AVSS AVSS f. CLAMPIN g. MODE h. REFSENSE i. VREF Figure 2. Equivalent Circuits CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. D AD9280 PIN CONFIGURATION 28-Lead Wide Body (SSOP) AVSS 1 DRVDD 2 NC 3 NC 4 D0 5 D1 6 28 AVDD 27 AIN 26 VREF 25 REFBS AD9280 24 REFBF TOP VIEW 23 MODE D2 7 (Not to Scale) 22 REFTF D3 8 D4 9 D5 10 D6 11 D7 12 OTR 13 DRVSS 14 21 REFTS 20 CLAMPIN 19 CLAMP 18 REFSENSE 17 STBY 16 THREE-STATE 15 CLK NC = NO CONNECT PIN FUNCTION DESCRIPTIONS SSOP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name AVSS DRVDD NC NC D0 D1 D2 D3 D4 D5 D6 D7 OTR DRVSS CLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN AVDD Description Analog Ground Digital Driver Supply No Connect No Connect Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7, Most Significant Bit Out-of-Range Indicator Digital Ground Clock Input HI: High Impedance State. LO: Normal Operation HI: Power-Down Mode. LO: Normal Operation Reference Select HI: Enable Clamp Mode. LO: No Clamp Clamp Reference Input Top Reference Top Reference Decoupling Mode Select Bottom Reference Decoupling Bottom Reference Internal Reference Output Analog Input Analog Supply REV. D -5- AD9280 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Offset Error Integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale." The point used as "zero" occurs 1/2 LSB before the first code transition. "Full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) The first transition should occur at a level 1 LSB above "zero." Offset is defined as the deviation of the actual first code transition from that point. Gain Error An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed. The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. Pipeline Delay (Latency) The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every rising edge. Typical Characterization Curves Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted) 1.0 (AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input 60 55 0.5 50 -0.5 AMPLITUDE 45 -6.0 AMPLITUDE 40 35 30 -20.0 AMPLITUDE 25 0 -0.5 SNR- dB 0 32 64 96 128 160 CODE OFFSET 192 224 240 DNL -1.0 20 1.00E+05 1.00E+06 1.00E+07 INPUT FREQUENCY - Hz 1.00E+08 Figure 3. Typical DNL Figure 5. SNR vs. Input Frequency 1.0 60 55 0.5 50 -0.5 AMPLITUDE 45 SINAD - dB -6.0 AMPLITUDE 40 35 30 -20.0 AMPLITUDE 25 INL 0 -0.5 -1.0 0 32 64 96 128 160 CODE OFFSET 192 224 240 20 1.00E+05 1.00E+06 1.00E+07 INPUT FREQUENCY - Hz 1.00E+08 Figure 4. Typical INL Figure 6. SINAD vs. Input Frequency -6- REV. D AD9280 -30 -35 105 100 -40 -45 THD - dB POWER CONSUMPTION - mW 95 -20.0 AMPLITUDE -50 -55 -60 -65 -0.5 AMPLITUDE -70 1.00E+05 1.00E+06 1.00E+07 INPUT FREQUENCY - Hz 1.00E+08 90 -6.0 AMPLITUDE 85 80 75 0 5 10 15 20 25 30 CLOCK FREQUENCY - MHz 35 40 Figure 7. THD vs. Input Frequency Figure 10. Power Consumption vs. Clock Frequency (MODE = AVSS) -80 -70 AIN = -0.5dBFS -60 1M 900k 800k 700k 1M THD - dB -50 HITS 600k 500k 400k 300k -40 -30 -20 200k -10 0 1.00E+06 100k 0 0 N-1 N CODE 0 N+1 1.00E+07 CLOCK FREQUENCY - Hz 1.00E+08 Figure 8. THD vs. Clock Frequency Figure 11. Grounded Input Histogram 1.01 CLOCK = 32MHz 1.009 30 20 10 0 -10 -20 FUND FIN = 1MHz FS = 32MHz VREF - V 1.008 -30 -40 -50 -60 -70 -80 -90 -100 -110 2nd3rd 5th 6th 4th 7th 9th 8th 1.007 1.006 1.005 -50 -30 -10 10 30 50 TEMPERATURE - C 70 90 -120 0E+0 4E+6 8E+6 12E+6 SINGLE-TONE FREQUENCY DOMAIN 16E+6 Figure 9. Voltage Reference Error vs. Temperature Figure 12. Single-Tone Frequency Domain REV. D -7- AD9280 0 -3 APPLYING THE AD9280 THEORY OF OPERATION SIGNAL AMPLITUDE - dB -6 -9 -12 -15 -18 -21 -24 1.0E+6 The AD9280 implements a pipelined multistage architecture to achieve high sample rate with low power. The AD9280 distributes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, the AD9280 requires a small fraction of the 256 comparators used in a traditional flash type A/D. A sampleand-hold function within each of the stages permits the first stage to operate on a new input sample while the second, third and fourth stages operate on the three preceding samples. 1.0E+7 1.0E+8 FREQUENCY - Hz 1.0E+9 OPERATIONAL MODES Figure 13. Full Power Bandwidth 50 40 30 20 10 A IB - REFBS = 0.5V REFTS = 2.5V CLOCK = 32MHz 0 -10 -20 -30 The AD9280 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation applications, including pin compatibility with the AD876-8 A/D. To realize this flexibility, internal switches on the AD9280 are used to reconfigure the circuit into different modes. These modes are selected by appropriate pin strapping. There are three parts of the circuit affected by this modality: the voltage reference, the reference buffer, and the analog input. The nature of the application will determine which mode is appropriate: the descriptions in the following sections, as well as Table I should assist in selecting the desired mode. -40 -50 0 0.5 1.5 1.0 2.0 INPUT VOLTAGE - V 2.5 3.0 Figure 14. Input Bias Current vs. Input Voltage Table I. Mode Selection Modes TOP/BOTTOM Input Connect AIN AIN CENTER SPAN AIN AIN Differential AIN Is Input 1 Input Span 1V 2V 1V 2V 1V MODE Pin AVDD AVDD REFSENSE Pin REF REFTS REFBS AGND AGND Figure 18 19 Short REFSENSE, REFTS and VREF Together AGND Short REFTS and VREF Together AVDD/2 AVDD/2 AVDD/2 AVDD/2 Short VREF and REFSENSE Together AVDD/2 AGND No Connect AVDD/2 20 AVDD/2 AVDD/2 29 AVDD/2 Short VREF and REFSENSE Together REFTS and REFBS Are Shorted Together for Input 2 2V External Ref AIN AVDD/2 AGND AVDD No Connect No Connect AVDD/2 AVDD/2 21, 22 2 V max AVDD AGND Span = REFTS - REFBS (2 V max) Short to VREFTF Short to 23 VREFBF Short to 30 VREFBF AD876-8 AIN 2V Float or AVSS AVDD No Connect Short to VREFTF -8- REV. D AD9280 SUMMARY OF MODES VOLTAGE REFERENCE 1 V Mode the internal reference may be set to 1 V by connecting REFSENSE and VREF together. 2 V Mode the internal reference my be set to 2 V by connecting REFSENSE to analog ground External Divider Mode the internal reference may be set to a point between 1 V and 2 V by adding external resistors. See Figure 16f. External Reference Mode enables the user to apply an external reference to REFTS, REFBS and VREF pins. This mode is attained by tying REFSENSE to VDD. REFERENCE BUFFER AIN REFTS SHA A/D CORE AD9280 REFBS Figure 15. AD9280 Equivalent Functional Input Circuit In single-ended operation, the input spans the range, REFBS AIN REFTS where REFBS can be connected to GND and REFTS connected to VREF. If the user requires a different reference range, REFBS and REFTS can be driven to any voltage within the power supply rails, so long as the difference between the two is between 1 V and 2 V. In differential operation, REFTS and REFBS are shorted together, and the input span is set by VREF, (REFTS - VREF/2) AIN (REFTS + VREF/2) where VREF is determined by the internal reference or brought in externally by the user. The best noise performance may be obtained by operating the AD9280 with a 2 V input range. The best distortion performance may be obtained by operating the AD9280 with a 1 V input range. REFERENCE OPERATION Center Span Mode midscale is set by shorting REFTS and REFBS together and applying the midscale voltage to that point The MODE pin is set to AVDD/2. The analog input will swing about that midscale point. Top/Bottom Mode sets the input range between two points. The two points are between 1 V and 2 V apart. The Top/Bottom Mode is enabled by tying the MODE pin to AVDD. ANALOG INPUT Differential Mode is attained by driving the AIN pin as one differential input, shorting REFTS and REFBS together and driving them as the second differential input. The MODE pin is tied to AVDD/2. Preferred mode for optimal distortion performance. Single-Ended is attained by driving the AIN pin while the REFTS and REFBS pins are held at dc points. The MODE pin is tied to AVDD. Single-Ended/Clamped (AC Coupled) the input may be clamped to some dc level by ac coupling the input. This is done by tying the CLAMPIN to some dc point and applying a pulse to the CLAMP pin. MODE pin is tied to AVDD. SPECIAL AD876-8 Mode enables users of the AD876-8 to drop the AD9280 into their socket. This mode is attained by floating or grounding the MODE pin. INPUT AND REFERENCE OVERVIEW The AD9280 can be configured in a variety of reference topologies. The simplest configuration is to use the AD9280's onboard bandgap reference, which provides a pin-strappable option to generate either a 1 V or 2 V output. If the user desires a reference voltage other than those two, an external resistor divider can be connected between VREF, REFSENSE and analog ground to generate a potential anywhere between 1 V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. A third alternative is to bring in top and bottom references, bypassing VREF altogether. Figures 16d, 16e and 16f illustrate the reference and input architecture of the AD9280. In tailoring a desired arrangement, the user can select an input configuration to match drive circuit. Then, moving to the reference modes at the bottom of the figure, select a reference circuit to accommodate the offset and amplitude of a full-scale signal. Table I outlines pin configurations to match user requirements. Figure 16, a simplified model of the AD9280, highlights the relationship between the analog input, AIN, and the reference voltages, REFTS, REFBS and VREF. Like the voltages applied to the resistor ladder in a flash A/D converter, REFTS and REFBS define the maximum and minimum input voltages to the A/D. The input stage is normally configured for single-ended operation, but allows for differential operation by shorting REFTS and REFBS together to be used as the second input. REV. D -9- AD9280 V* +FS -FS AIN SHA 10k 10k A2 10k -F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF 10k REFBF A/D CORE 4.2k TOTAL 0.1 F 10 F MIDSCALE AIN SHA AD9280 MODE AVDD/2 0.1 F AD9280 +F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF REFTS REFBS MODE (AVDD) REFTF 0.1 F REFTS 10k 10k REFTF A2 REFBS 10k INTERNAL REF 10k A/D CORE 4.2k TOTAL 0.1 F 10 F 0.1 F REFBF 0.1 F MIDSCALE OFFSET VOLTAGE IS DERIVED FROM INTERNAL OR EXTERNAL REF * MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE a. Top/Bottom Mode MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO V AIN AVDD/2 10k 10k REFTS REFBS 10k INTERNAL REF 10k A2 A/D CORE 4.2k TOTAL b. Center Span Mode AD9280 SHA MODE AVDD/2 0.1 F REFTF 0.1 F 10 F 0.1 F REFBF c. Differential Mode VREF (2V) A1 1V VREF (1V) 1V 0.1 F REFSENSE 1.0 F A1 10k REFSENSE 0.1 F 1.0 F AD9280 AVSS AD9280 10k AVSS d. 1 V Reference e. 2 V Reference A1 1V VREF (= 1 + RA/RB) RA REFSENSE RB 0.1 F 1.0 F A1 1V REFSENSE AVDD VREF AD9280 INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF RA AND RB. AVSS AD9280 f. Variable Reference (Between 1 V and 2 V) g. Internal Reference Disable (Power Reduction) Figure 16. -10- REV. D AD9280 The actual reference voltages used by the internal circuitry of the AD9280 appear on REFTF and REFBF. For proper operation, it is necessary to add a capacitor network to decouple these pins. The REFTF and REFBF should be decoupled for all internal and external configurations as shown in Figure 17. Figure 19 shows the single-ended configuration for 2 V p-p operation. REFSENSE is connected to GND, resulting in a 2 V reference output. 2V 0V AIN SHA 10k REFTS REFBS 10k 10k 10k A2 A/D CORE 4.2k TOTAL 0.1 F 10 F AD9280 MODE AVDD 0.1 F REFTF 10 F 0.1 F REFTF AD9280 REFBF 0.1 F 0.1 F 0.1 F REFBF Figure 17. Reference Decoupling Network VREF Note: REFTF = reference top, force REFBF = reference bottom, force REFTS = reference top, sense REFBS = reference bottom, sense INTERNAL REFERENCE OPERATION A1 1V 1.0 F 0.1 F REF SENSE Figures 18, 19 and 20 show sample connections of the AD9280 internal reference in its most common configurations. (Figures 18 and 19 illustrate top/bottom mode while Figure 20 illustrates center span mode). Figure 29 shows how to connect the AD9280 for 1 V p-p differential operation. Shorting the VREF pin directly to the REFSENSE pin places the internal reference amplifier, A1, in unity-gain mode and the resultant reference output is 1 V. In Figure 18 REFBS is grounded to give an input range from 0 V to 1 V. These modes can be chosen when the supply is either +3 V or +5 V. The VREF pin must be bypassed to AVSS (analog ground) with a 1.0 F tantalum capacitor in parallel with a low inductance, low ESR, 0.1 F ceramic capacitor. 1V 0V 10k AIN SHA Figure 19. Internal Reference, 2 V p-p Input Span (Top/Bottom Mode) Figure 20 shows the single-ended configuration that gives the good high frequency dynamic performance (SINAD, SFDR). To optimize dynamic performance, center the common-mode voltage of the analog input at approximately 1.5 V. Connect the shorted REFTS and REFBS inputs to a low impedance 1.5 V source. In this configuration, the MODE pin is driven to a voltage at midsupply (AVDD/2). Maximum reference drive is 1 mA. An external buffer is required for heavier loads. 2V AIN AD9280 SHA 10k MODE AD9280 1V AVDD/2 MODE AVDD 0.1 F +1.5V 10k REFTF 0.1 F REFTF REFTS REFBS REFTS REFBS 10k A2 10k 10k REFBF A2 A/D CORE 10k 10k 4.2k TOTAL 0.1 F 10 F A/D CORE 4.2k TOTAL 0.1 F 10 F 0.1 F 0.1 F VREF A1 1V REF SENSE REFBF VREF A1 1.0 F 0.1 F 1.0 F 0.1 F 1V REF SENSE Figure 20. Internal Reference 1 V p-p Input Span (Center Span Mode) Figure 18. Internal Reference--1 V p-p Input Span (Top/Bottom Mode) REV. D -11- AD9280 EXTERNAL REFERENCE OPERATION Using an external reference may provide more flexibility and improve drift and accuracy. Figures 21 through 23 show examples of how to use an external reference with the AD9280. To use an external reference, the user must disable the internal reference amplifier by connecting the REFSENSE pin to VDD. The user then has the option of driving the VREF pin, or driving the REFTS and REFBS pins. The AD9280 contains an internal reference buffer (A2), that simplifies the drive requirements of an external reference. The external reference must simply be able to drive a 10 k load. Figure 21 shows an example of the user driving the top and bottom references. REFTS is connected to a low impedance 2 V source and REFBS is connected to a low impedance 1 V source. REFTS and REFBS may be driven to any voltage within the supply as long as the difference between them is between 1 V and 2 V. 2V 1V 10k REFTS REFBS 10k REF SENSE AVDD MODE 10k REFBF 10k A2 A/D CORE 4.2k TOTAL 0.1 F 10 F AIN SHA Figure 23a shows an example of the external references driving the REFTF and REFBF pins that is compatible with the AD876. REFTS is shorted to REFTF and driven by an external 4 V low impedance source. REFBS is shorted to REFBF and driven by a 2 V source. The MODE pin is connected to GND in this configuration. 4V VIN 2V 4V 10 F 2V 0.1 F 0.1 F 0.1 F REFTS REFTF AD9280 REFBF REFBS VREF AVDD REFSENSE MODE AD9280 Figure 23a. External Reference--2 V p-p Input Span REFTF 0.1 F 2V 1V REFTS +5V 6 REFT 5 8 7 C3 0.1 F C2 10 F C5 0.1 F 6 REFB 3 4 C1 0.1 F REFBF C6 0.1 F C4 0.1 F REFTF 0.1 F AD9280 REFBS 2 Figure 21. External Reference Mode--1 V p-p Input Span Figure 22 shows an example of an external reference generating 2.5 V at the shorted REFTS and REFBS inputs. In this instance, a REF43 2.5 V reference drives REFTS and REFBS. A resistive divider generates a 1 V VREF signal that is buffered by A3. A3 must be able to drive a 10 k, capacitive load. Choose this op amp based on noise and accuracy requirements. Figure 23b. Kelvin Connected Reference Using the AD9280 STANDBY OPERATION 3.0V 2.5V 2.0V AD9280 AIN REFTS REFBS 0.1 F REFTF VREF 1.0 F 0.1 F 0.1 F REFBF AVDD/2 +5V AVDD MODE REFSENSE 0.1 F 10 F AVDD AVDD The ADC may be placed into a powered down (sleep) mode by driving the STBY (standby) pin to logic high potential and holding the clock at logic low. In this mode the typical power drain is approximately 4 mW. The ADC will "wake up" in 400 ns (typ) after the standby pulse goes low. CLAMP OPERATION 10 F 1.5k A3 0.1 F 0.1 F 1k REF43 0.1 F Figure 22. External Reference Mode--1 V p-p Input Span 2.5 VCM The AD9280ARS features an optional clamp circuit for dc restoration of video or ac coupled signals. Figure 24 shows the internal clamp circuitry and the external control signals needed for clamp operation. To enable the clamp, apply a logic high to the CLAMP pin. This will close the switch SW1. The clamp amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN pin. After the desired clamp level is attained, SW1 is opened by taking CLAMP back to a logic low. Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the dc voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 , to maintain the closed-loop stability of the clamp amplifier. -12- REV. D AD9280 The allowable voltage range that can be applied to CLAMPIN depends on the operational limits of the internal clamp amplifier. The recommended clamp range is between 0.5 volts and 2.0 volts. The input capacitor should be sized to allow sufficient acquisition time of the clamp voltage at AIN within the CLAMP interval, but also be sized to minimize droop between clamping intervals. Specifically, the acquisition time when the switch is closed will equal: T ACQ = RIN CIN V ln C VE back porch to truncate the SYNC below the AD9280's minimum input voltage. With a CIN = 1 F, and RIN = 20 , the acquisition time needed to set the input dc level to one volt with 1 mV accuracy is about 140 s, assuming a full 1 volt VC. With a 1 F input coupling capacitor, the droop across one horizontal can be calculated: IBIAS = 22 A, and t = 63.5 s, so dV = 1.397 mV, which is less than one LSB. After the input capacitor is initially charged, the clamp pulse width only needs to be wide enough to correct small voltage errors such as the droop. The fine scale settling characteristics of the clamp circuitry are shown in Table II. Depending on the required accuracy, a CLAMP pulse width of 1 s-3 s should work in most applications. The OFFSET values ignore the contribution of offset from the clamp amplifier; they simply compare the output code with a "final value" measured with a much longer CLAMP pulse duration. Table II. where VC is the voltage change required across CIN, and VE is the error voltage. VC is calculated by taking the difference between the initial input dc level at the start of the clamp interval and the clamp voltage supplied at CLAMPIN. VE is a system dependent parameter, and equals the maximum tolerable deviation from VC. For example, if a 2-volt input level needs to be clamped to 1 volt at the AD9280's input within 10 millivolts, then VC equals 2 - 1 or 1 volt, and VE equals 10 mV. Note that once the proper clamp level is attained at the input, only a very small voltage change will be required to correct for droop. The voltage droop is calculated with the following equation: CLAMP 8 s 4 s 3 s 2 s 1 s OFFSET <1 LSB <2 LSBs 2 LSBs 5 LSBs 9 LSBs dV = I BIAS t CIN () where t = time between clamping intervals. The bias current of the AD9280 will depend on the sampling rate, FS, and the difference between the reference midpoint, (REFTS-REFBS)/2 and the input voltage. For a fixed sampling rate of 32 MHz, Figure 14 shows the input bias current for a given input. For a 1 V input range, the maximum input bias current from Figure 14 is 22 A. For lower sampling rates the input bias current will scale proportionally. If droop is a critical parameter, then the minimum value of CIN should be calculated first based on the droop requirement. Acquisition time--the width of the CLAMP pulse--can be adjusted accordingly once the minimum capacitor value is chosen. A tradeoff will often need to be made between droop and acquisition time, or error voltage VE. Clamp Circuit Example AD9280 CLAMP IN CLAMP CIN RIN AIN SW1 TO SHA Figure 24a. Clamp Operation AIN 0.1 F REFTF REFTS 10 F 0.1 F 0.1 F A single supply video amplifier outputs a level-shifted video signal between 2 and 3 volts with the following parameters: horizontal period = 63.56 s, horizontal sync interval = 10.9 s, horizontal sync pulse = 4.7 s, sync amplitude = 0.3 volts, video amplitude of 0.7 volts, reference black level = 2.3 volts The video signal must be dc restored from a 2- to 3-volt range down to a 1- to 2-volt range. Configuring the AD9280 for a one volt input span with an input range from 1 to 2 volts (see Figure 24), the CLAMPIN voltage can be set to 1 volt with an external voltage or by direct connection to REFBS. The CLAMP pulse may be applied during the SYNC pulse, or during the AD9280 REFBF REFBS AVDD 2 MODE CLAMP SHORT TO REFBS OR EXTERNAL DC CLAMPIN Figure 24b. Video Clamp Circuit REV. D -13- AD9280 DRIVING THE ANALOG INPUT Figure 25 shows the equivalent analog input of the AD9280, a sample-and-hold amplifier (switched capacitor input SHA). Bringing CLK to a logic low level closes Switches 1 and 2 and opens Switch 3. The input source connected to AIN must charge capacitor CH during this time. When CLK transitions from logic "low" to logic "high," Switches 1 and 2 open, placing the SHA in hold mode. Switch 3 then closes, forcing the output of the op amp to equal the voltage stored on CH. When CLK transitions from logic "high" to logic "low," Switch 3 opens first. Switches 1 and 2 close, placing the SHA in track mode. The structure of the input SHA places certain requirements on the input drive source. The combination of the pin capacitance, CP, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to 8-bit accuracy in one half of a clock cycle. When the SHA goes into track mode, the input source must charge or discharge capacitor CH from the voltage already stored on CH to the new voltage. In the worst case, a full-scale voltage step on the input, the input source must provide the charging current through the RON (50 ) of Switch 1 and quickly (within 1/2 CLK period) settle. This situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously stored on CH, the hold capacitor requires no input current and the equivalent input impedance is extremely high. Adding series resistance between the output of the source and the AIN pin reduces the drive requirements placed on the source. Figure 26 shows this configuration. The bandwidth of the particular application limits the size of this resistor. To maintain the performance outlined in the data sheet specifications, the resistor should be limited to 20 or less. For applications with signal bandwidths less than 16 MHz, the user may proportionally increase the size of the series resistor. Alternatively, adding a shunt capacitance between the AIN pin and analog ground can lower the ac load impedance. The value of this capacitance will depend on the source resistance and the required signal bandwidth. The input span of the AD9280 is a function of the reference voltages. For more information regarding the input range, see the Internal and External Reference sections of the data sheet. CH In many cases, particularly in single-supply operation, ac coupling offers a convenient way of biasing the analog input signal at the proper signal range. Figure 27 shows a typical configuration for ac-coupling the analog input signal to the AD9280. Maintaining the specifications outlined in the data sheet requires careful selection of the component values. The most important is the f -3 dB high-pass corner frequency. It is a function of R2 and the parallel combination of C1 and C2. The f -3 dB point can be approximated by the equation: f -3 dB = 1/(2 x pi x [R2] CEQ) where CEQ is the parallel combination of C1 and C2. Note that C1 is typically a large electrolytic or tantalum capacitor that becomes inductive at high frequencies. Adding a small ceramic or polystyrene capacitor (on the order of 0.01 F) that does not become inductive until negligibly higher frequencies, maintains a low impedance over a wide frequency range. NOTE: AC coupled input signals may also be shifted to a desired level with the AD9280's internal clamp. See Clamp Operation. C1 VIN R2 C2 VBIAS R1 AIN IB AD9280 Figure 27. AC Coupled Input There are additional considerations when choosing the resistor values. The ac-coupling capacitors integrate the switching transients present at the input of the AD9280 and cause a net dc bias current, IB, to flow into the input. The magnitude of the bias current increases as the signal magnitude deviates from V midscale and the clock frequency increases; i.e., minimum bias current flow when AIN = V midscale. This bias current will result in an offset error of (R1 + R2) x IB. If it is necessary to compensate this error, consider making R2 negligibly small or modifying VBIAS to account for the resultant offset. In systems that must use dc coupling, use an op amp to levelshift a ground-referenced signal to comply with the input requirements of the AD9280. Figure 28 shows an AD8041 configured in noninverting mode. +VCC AIN S1 CP S3 (REFTS REFBS) CP S2 CH SHA 0.1 F NC 0VDC 1V p-p 2 7 1 20 6 AIN AD9280 AD8041 AD9280 3 MIDSCALE OFFSET VOLTAGE 4 5 NC Figure 25. AD9280 Equivalent Input Structure < 20 AIN VS Figure 28. Bipolar Level Shift AD9280 Figure 26. Simple AD9280 Drive Configuration -14- REV. D AD9280 DIFFERENTIAL INPUT OPERATION The AD9280 will accept differential input signals. This function may be used by shorting REFTS and REFBS and driving them as one leg of the differential signal (the top leg is driven into AIN). In the configuration below, the AD9280 is accepting a 1 V p-p signal. See Figure 29. AD9280 AIN 1V AVDD/2 REFTS 0.1 F REFBS 0.1 F VREF 1.0 F 0.1 F 2V 0.1 F REFTF 10 F The pipelined architecture of the AD9280 operates on both rising and falling edges of the input clock. To minimize duty cycle variations the recommended logic family to drive the clock input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 32 MSPS operation. The AD9280 is designed to support a conversion rate of 32 MSPS; running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, some slight performance improvements might be realized by clocking the AD9280 at slower clock rates. S1 ANALOG INPUT S2 REFBF tC tCH tCL S4 S3 REFSENSE AVDD/2 MODE INPUT CLOCK 25ns Figure 29. Differential Input AD876-8 MODE OF OPERATION DATA OUTPUT DATA 1 The AD9280 may be dropped into the AD876-8 socket. This will allow AD876-8 users to take advantage of the reduced power consumption realized when running the AD9280 on a 3.0 V analog supply. Figure 30 shows the pin functions of the AD876-8 and AD9280. The grounded REFSENSE pin and floating MODE pin effectively put the AD9280 in the external reference mode. The external reference input for the AD876-8 will now be placed on the reference pins of the AD9280. The clamp controls will be grounded by the AD876-8 socket. The AD9280 has a 3 clock cycle delay compared to a 3.5 cycle delay of the AD876-8. 4V AIN 2V 4V 10 F 2V 0.1 F 0.1 F NC AVDD 0.1 F REFBF REFBS MODE REFSENSE CLAMP CLAMPIN OTR VREF 0.1 F Figure 31. Timing Diagram The power dissipated by the output buffers is largely proportional to the clock frequency; running at reduced clock rates provides a reduction in power consumption. DIGITAL INPUTS AND OUTPUTS Each of the AD9280 digital control inputs, THREE-STATE and STBY are reference to analog ground. The clock is also referenced to analog ground. The format of the digital output is straight binary (see Figure 32). A low power mode feature is provided such that for STBY = HIGH and the clock disabled, the static power of the AD9280 will drop below 5 mW. OTR AD9280 REFTS REFTF -FS+1LSB -FS +FS +FS-1LSB Figure 32. Output Data Format Figure 30. AD876 Mode CLOCK INPUT THREESTATE tDHZ DATA (D0-D9) HIGH IMPEDANCE tDEN The AD9280 clock input is buffered internally with an inverter powered from the AVDD pin. This feature allows the AD9280 to accommodate either +5 V or +3.3 V CMOS logic input signal swings with the input threshold for the CLK pin nominally at AVDD/2. Figure 33. Three-State Timing Diagram REV. D -15- AD9280 APPLICATIONS DIRECT IF DOWN CONVERSION USING THE AD9280 Sampling IF signals above an ADC's baseband region (i.e., dc to FS/2) is becoming increasingly popular in communication applications. This process is often referred to as Direct IF Down Conversion or Undersampling. There are several potential benefits in using the ADC to alias (i.e., or mix) down a narrowband or wideband IF signal. First and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters, reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. A detailed discussion on using this technique in digital receivers can be found in Analog Devices Application Notes AN-301 and AN-302. In Direct IF Down Conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will downconvert an IF signal. Similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the ADC's baseband region. A tradeoff exists between the complexity of this image rejection filter and the sample rate as well as dynamic range of the ADC. The AD9280 is well suited for various narrowband IF sampling applications. The AD9280's low distortion input SHA has a full-power bandwidth extending to 300 MHz thus encompassing many popular IF frequencies. The AD9280 will typically yield an improvement in SNR when configured for the 2 V span, the 1 V span provides the optimum full-scale distortion performance. Furthermore, the 1 V span reduces the performance requirements of the input driver circuitry and thus may be more practical for system implementation purposes. Figure 34 shows a simplified schematic of the AD9280 configured in an IF sampling application. To reduce the complexity of the digital demodulator in many quadrature demodulation applications, the IF frequency and/or sample rate are selected such that the bandlimited IF signal aliases back into the center of the ADC's baseband region (i.e., FS/4). For example, if an IF signal centered at 45 MHz is sampled at 20 MSPS, an image of this IF signal will be aliased back to 5.0 MHz which corresponds to one quarter of the sample rate (i.e., FS/4). This demodulation technique typically reduces the complexity of the post digital demodulator ASIC which follows the ADC. To maximize its distortion performance, the AD9280 is configured in the differential mode with a 1 V span using a transformer. The center tap of the transformer is biased at midsupply via a resistor divider. Preceding the AD9280 is a bandpass filter as well as a 32 dB gain stage. A large gain stage may be required to compensate for the high insertion losses of a SAW filter used for image rejection. The gain stage will also provide adequate isolation for the SAW filter from the charge "kick back" currents associated with AD9280's input stage. The gain stage can be realized using one or two cascaded AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz, current-feedback op amp having a 3rd order intercept characterized up to 250 MHz. A passive bandpass filter following the AD8009 attenuates its dominant 2nd order distortion products which would otherwise be aliased back into the AD9280's baseband region. Also, it reduces any out-of-band noise which would also be aliased back due to the AD9280's noise bandwidth of 220+ MHz. Note, the bandpass filters specifications are application dependent and will affect both the total distortion and noise performance of this circuit. The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC for a narrowband IF sampling application. Both single-tone and dual-tone SFDR vs. amplitude are very useful in assessing an ADC's noise performance and noise contribution due to aperture jitter. In any application, one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device. G1 = 20dB SAW FILTER OUTPUT 50 200 22.1 50 G2 = 12dB L-C BANDPASS FILTER MINI CIRCUITS T4 - 6T 1:4 200 AD9280 AIN REFTS REFBS 50 280 93.1 VREF 1.0 F 1k AVDD 1k 0.1 F 0.1 F REFSENSE Figure 34. Simplified AD9280 IF Sampling Circuit -16- REV. D AD9280 Figures 35-38 combine the dual-tone SFDR as well as single tone SFDR and SNR performance at IF frequencies of 45 MHz, 70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. amplitude data is referenced to dBFS while the single tone SNR data 70 DUAL TONE SFDR 60 is referenced to dBc. The AD9280 was operated in the differential mode (via transformer) with a 1 V span. The analog supply (AVDD) and the digital supply (DRVDD) were set to +5 V and 3.3 V, respectively. 80 70 WORST CASE SPURIOUS - dBFS SNR - dBc SINGLE TONE SFDR WORST CASE SPURIOUS - dBFS SNR - dBc SINGLE TONE SFDR 50 40 60 DUAL TONE SFDR 50 40 30 SNR 20 10 0 -0.5 CLK = 30.9MHz SINGLE TONE = 85.5MHz DUAL TONE F1 = 84.5MHz F2 = 85.5MHz 30 SNR 20 10 0 -0.5 CLK = 25.7MHz SINGLE TONE = 45.5MHz DUAL TONE F1 = 44.5MHz F2 = 45.5MHz -5 -10 -15 -20 -25 -30 INPUT POWER LEVEL - dBFS -35 -40 -5 -10 -15 -20 -25 -30 INPUT POWER LEVEL - dBFS -35 -40 Figure 35. SNR/SFDR for IF @ 45 MHz Figure 37. SNR/SFDR for IF @ 85 MHz 70 DUAL TONE SFDR 60 70 SINGLE TONE SFDR 60 WORST CASE SPURIOUS - dBFS SNR - dBc WORST CASE SFDR - dBFS SNR - dBc SINGLE TONE SFDR 50 40 DUAL TONE SFDR 50 40 30 SNR 20 10 0 -0.5 CLK = 31.1MHz SINGLE TONE = 70.5MHz DUAL TONE F1 = 69.5MHz F2 = 70.5MHz -5 -10 -15 -20 -25 -30 INPUT POWER LEVEL - dBFS -35 -40 30 SNR 20 10 0 -0.5 FS = 32MHz SINGLE TONE = 135.5MHz F1 = 134.5MHz F2 = 135.5MHz -5 -10 -15 -20 -25 -30 INPUT POWER LEVEL - dBFS -35 -40 Figure 36. SNR/SFDR for IF @ 70 MHz Figure 38. SNR/SFDR for IF @ 135 MHz REV. D -17- AD9280 R10 5k +3-5A R7 5.49k TP14 XXXX ADJ. R8 10k 2 3 CW R9 1.5k C8 10/10V +3-5A R13 11k R12 10k XXXX ADJ. CW 2 3 C9 10/10V U3 8 CM R20 178 TP17 U2 8 R11 15k +3-5A 5 1 C7 0.1 F 6 AD822 4 AD822 U2 7 R15 1k R17 316 Q1 2N3906 0.626V TO 4.8V TP16 D1 AD1580 EXTT C11 0.1 F R19 178 C12 0.1 F C13 10/10V AD822 4 1 C10 0.1 F 6 5 C29 0.1 F AD822 U3 7 R16 1k R18 316k Q2 2N3904 C14 0.1 F C15 10/10V EXTB TP11 J7 JP5 +3-5A CLAMP R53 49.9 R37 1k JP17 R38 1k GND JP18 R39 1k 7 AVDD C16 0.1 F C17 10/10V 28 AVDD 2 DRVDD C19 0.1 F C18 10/10V OTR TP19 WHITE 13 3 4 5 6 7 8 9 10 11 12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 16 15 21 20 19 18 17 14 24 23 22 13 8 9 3 4 5 6 7 10 1 2 11 12 5 12 RN1 22 D5 D6 D7 D8 D9 DRVDD C40 0.1 F GND GND B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A VCCB VCCA NC1 T/R GD2 OE GD1 U4 GD3 4 13 RN1 22 2 B1 +3-5D C20 0.1 F GND 3 CLK D0 D1 D2 D3 D4 DRVDD C41 0.1 F GND 19 20 21 18 17 16 15 14 24 23 22 13 U5 B A U5 B A U5 B A U5 B A U5 B A U5 B A U5 B A U5 B A VCCB VCCA NC1 T/R GD2 OE GD1 U5 GD3 5 4 3 6 7 8 9 10 1 2 11 12 2 JP21 1 3 A GND +3-5D C42 0.1 F S2 15 RN1 22 1 16 RN1 22 CLK WHITE 6 11 RN2 22 5 12 RN2 22 4 +3-5D C21 0.1 F GND 2 JP20 GND 1 C43 0.1 F GND 2 15 RN2 22 1 16 RN2 22 15 J8 13 RN2 22 3 RN2 22 17 J8 14 NC 19 J8 NC 21 J8 33 J8 CLK_OUT 23 J8 NC 1 J8 5 J8 7 J8 DRVDD 10 RN1 22 6 11 RN1 22 9 J8 11 J8 13 J8 27 J8 25 J8 3 2 4 6 8 J8 J8 J8 J8 J8 DRVDD B1 3 B1 3 S3 2 A S4 2 A THREE-STATE STBY AD9280 U1 DUTCLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN C33 + 10/10V 15 16 17 18 19 20 21 22 23 24 25 26 27 OTR NC CLK THREE-STATE NC BIT0 STBY BIT1 REFSENSE BIT2 CLAMP BIT3 CLAMPIN BIT4 REFTS BIT5 REFTF BIT6 MODE BIT7 REFBF REFBS VREF AIN AVSS 1 DRVSS 14 10 J8 12 J8 14 J8 16 J8 18 J8 20 J8 22 J8 24 J8 26 J8 39 J8 28 J8 29 J8 30 J8 31 J8 32 J8 34 J8 35 J8 36 J8 37 J8 38 J8 40 J8 2 74LVXC4245WM NOTE: THE AD9280 IS EXERCISED IN AN AD9200 EVALUATION BOARD GND 74LVXC4245WM 3 Figure 39a. Evaluation Board Schematic -18- REV. D AD9280 JP1 AVDD TP1 JP2 C3 0.1 F C5 10/10V REFSENSE JP10 TP3 EXTB AVDD R5 10k JP15 REFTF C6 0.1 F TP5 S5 2 TP6 JP11 GND EXTT CLAMPIN EXTT REFTS JP12 TP7 JP7 T1-1T J1 2 S8 R1 49.9 A 3 1B TP8 JP8 C1 0.1 F 2 C2 47/10V S1 JP26 6 P S JP14 REFBF JP3 JP4 VREF B 1 3 A JP6 JP9 + TP4 C4 0.1 F MODE R6 10k JP16 GND GND C37 C38 C36 C35 10/10V 0.1 F 0.1 F 0.1 F REFBS JP13 GND EXTB AIN 3 AVDD JP22 AVDDCLK R35 4.99k R34 2k R36 4.99k CW 1 U6 2 5 U6 6 4 2 TP12 1B C30 0.1 F J5 CM ADC_CLK 1B 3 A CLK R4 49.9 3 U6 4 R52 49.9 TP13 DUTCLK S6 2 R51 49.9 1 R2 100 TP9 T1 REFBS S7 2 3 A A 3 1 B R3 100 TP10 DCIN TP29 L4 J9 TP20 C32 0.1 F L1 J2 TP21 C22 0.1 F L2 J3 TP22 C24 0.1 F L3 J4 C26 0.1 F C27 10/10V +3-5A C25 33/16V AVDD C23 10/10V DRVDD 14 74AHC14 PWR U6 GND 7 11 C28 0.1 F U6 10 C31 10/10V U6 DECOUPLING AVDDCLK 9 U6 8 +3-5D 13 U6 12 TP23 TP24 TP25 TP26 TP27 TP28 GND J6 GND J10 Figure 39b. Evaluation Board Schematic REV. D -19- AD9280 Figure 40a. Evaluation Board, Component Signal (Not to Scale) Figure 40b. Evaluation Board, Solder Signal (Not to Scale) -20- REV. D AD9280 Figure 40c. Evaluation Board Power Plane (Not to Scale) Figure 40d. Evaluation Board Ground Plane (Not to Scale) REV. D -21- AD9280 Figure 40e. Evaluation Board Component Silk (Not to Scale) C33 C6 C18 C19 C4 C5 C3 C16 C17 Figure 40f. Evaluation Board Solder Silk (Not to Scale) -22- REV. D AD9280 GROUNDING AND LAYOUT RULES DIGITAL OUTPUTS As is the case for any high performance device, proper grounding and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD9280 have been separated to optimize the management of return currents in a system. Grounds should be connected near the ADC. It is recommended that a printed circuit board (PCB) of at least four layers, employing a ground plane and power planes, be used with the AD9280. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD9280 in a solid ground plane. The power and ground return currents must be carefully managed. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. Each of the on-chip buffers for the AD9280 output bits (D0-D7) is powered from the DRVDD supply pins, separate from AVDD. The output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated. In all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level. For DRVDD = 5 V, the AD9280 output signal swing is compatible with both high speed CMOS and TTL logic families. For TTL, the AD9280 on-chip, output drivers were designed to support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 32 MSPS, other TTL families may be appropriate. For interfacing with lower voltage CMOS logic, the AD9280 sustains 32 MSPS operation with DRVDD = 3 V. In all cases, check your logic family data sheets for compatibility with the AD9280 Digital Specification table. THREE-STATE OUTPUTS The digital outputs of the AD9280 can be placed in a high impedance state by setting the THREE-STATE pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation. REV. D -23- AD9280 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 0.311 (7.9) 0.301 (7.64) 1 14 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.79) 0.066 (1.67) 0.212 (5.38) 0.205 (5.21) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 8 0.015 (0.38) SEATING 0.009 (0.229) 0 0.010 (0.25) PLANE 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) -24- REV. D PRINTED IN U.S.A. C3118d-0-8/99 |
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